1. Technical Field
The present invention relates in general to a method and apparatus for data processing and in particular to data processing within an in-order completion processor. Still more particularly, the present invention relates to a method for executing instructions within an in-order completion processor and an improved instruction reservation table within an execution unit of an in-order completion processor.
2. Description of the Related Art
State-of-the-art superscalar processors include a number of execution units which each execute instructions belonging to a particular class of instructions. For example, a typical superscalar processor includes a fixed-point unit (FXU) for executing fixed-point instructions, a floating-point unit (FPU) for executing floating-point instructions, and a load/store unit for loading data from and storing data to memory. During each processor cycle, one or more instructions within a particular class of instructions are dispatched to each of the multiple execution units. Because each execution unit contains limited execution resources (e.g., a typical FXU has one adder, one multiplier, and one logical unit) and because operands for instructions may not be immediately available following dispatch, each execution unit provides facilities known as a reservation table (station) which stores instructions within the execution unit until the instructions are executed.
Referring now to FIG. 4, there is depicted a conventional reservation table within an execution unit of a superscalar processor which employs a renaming architecture. Reservation table 200 includes a number of entries 202, which each store an instruction in association with an instruction ID, rA tag, rB tag, and rD tag. The instruction ID is utilized by the processor to track the program order of instructions throughout the stages of execution. The rA tag and rB tag associated with an instruction indicate the sources of the A and B operands of an instruction, respectively. For example, if the execution unit is a FXU, the rA tag and rB tag of an instruction specify which general purpose registers (GPR) or GPR rename buffers are the sources of the A and B operands of the instruction. Conversely, the rA and rB tags specify which floating-point registers (FPR) or FPR rename buffers are the sources of the A and B operands if the execution unit is a FPU. The rD tag specifies the destination GPR or FPR rename buffer into which the result of the instruction will be stored. Finally, each entry 202 has an operand field for storing operands of the instruction. As illustrated, operands are loaded from the sources specified by the rA and rB tags into the operand field of an entry 202 as soon as the operands become valid. When both the A and B operands of an instruction are loaded into the operand field of an entry 202, execution logic 204 selects the instruction within that entry 202 as the next instruction to be executed by the execution unit.
Although the design of reservation table 200 provides a high performance interface between the execution unit and the operand sources within the processor, reservation table 200 is expensive in terms of the processor chip area required by reservation table 200 to store operands. For example, if the processor utilizes 64 bit operands, 128 bits of storage are required for the operand field of each entry 202 within reservation table 200. In high performance processors which dispatch a large number of instructions each cycle, thereby requiring a deep reservation table, the processor chip area allocated to the reservation table is particularly significant.
Consequently, it would be desirable to provide an improved reservation table within an execution unit of a processor and an improved method for executing instructions within an execution unit of a processor, such that the processor chip area consumed by the reservation table is reduced.